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PIC18CXX8
DS30475A-page 138
Advanced Information
2000 Microchip Technology Inc.
REGISTER 15-2:
SSPCON1 REGISTER
R/W-0
WCOL
SSPOV
SSPEN
CKP
SSPM3
SSPM2
SSPM1
SSPM0
bit 7
bit 0
bit 7
WCOL: Write Collision Detect bit
Master mode:
1
= A write to the SSPBUF register was attempted while the I2C conditions were not valid for a
transmission to be started
0
= No collision
Slave mode:
1
= The SSPBUF register is written while it is still transmitting the previous word (must be
cleared in software)
0
= No collision
bit 6
SSPOV: Receive Overflow Indicator bit
In SPI mode:
1
= A new byte is received while the SSPBUF register is still holding the previous data. In case
of overflow, the data in SSPSR is lost. Overflow can only occur in Slave mode. In Slave
mode, the user must read the SSPBUF, even if only transmitting data, to avoid setting
overflow. In Master mode, the overflow bit is not set since each new reception (and
transmission) is initiated by writing to the SSPBUF register. (Must be cleared in software.)
0
= No overflow
In I2C mode:
1
= A byte is received while the SSPBUF register is still holding the previous byte. SSPOV is a
"don’t care" in Transmit mode. (Must be cleared in software.)
0
= No overflow
bit 5
SSPEN: Synchronous Serial Port Enable bit
In both modes, when enabled, these pins must be properly configured as input or output.
In SPI mode:
1
= Enables serial port and configures SCK, SDO, SDI, and SS as the source of the serial port
pins
0
= Disables serial port and configures these pins as I/O port pins
In I2C mode:
1
= Enables the serial port and configures the SDA and SCL pins as the source of the serial
port pins
0
= Disables serial port and configures these pins as I/O port pins
bit 4
CKP: Clock Polarity Select bit
In SPI mode:
1
= Idle state for clock is a high level
0
= Idle state for clock is a low level
In I2C Slave mode:
SCK release control
1
= Enable clock
0
= Holds clock low (clock stretch). (Used to ensure data setup time.)
In I2C Master mode
Unused in this mode
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